A Comparative Analysis and Ideas to Reduce Various Leakage Power in Modern VLSI

In today's high-performance chips, comparative analysis and ideas for reducing power consumption have become the dominant factor in overall power consumption. This should reduce the power consumption of high-density chips, which is so great that many new techniques have been developed in the proposal to design low-power circuits and systems. Ultra-thin gate oxides, very low threshold voltages, and short channels are hallmarks of nanoscale chips. Therefore, the most difficult problem that arises in VLSI circuits and systems is power dissipation. This paper provides an overview of sources of leakage currents in sub-micrometer CMOS gates and techniques, limitations, analysis and ideas to reduce leakage currents [1]; an overview of current circuit-level leakage currents [2] for various techniques; also discusses an example of a 1-bit adiabatic ECRL adder which compares the power and delay. This is one way of leakage minimization technique which is caused by switching action. This simulation work is done in cadence tool using FINFET technology which is a very fast-growing technology as compared to CMOS technology [3]. 

Keywords: Leakage power, Ultra-thin gate oxide, Very low threshold voltage and short channel.